The present invention is related to a process of manufacturing a read-only-memory (ROM), and more particularly to a process of manufacturing a read-only-memory with self-aligned ROM coding.
Read-only-memory had been intensively used among digital equipments like mini-computers, and microprocessor systems, for storing invariable programs and/or data for system operation. Since read-only-memory is non-volatile, usually a client first sends his program to a ROM manufacturing factory, then the program is built or coded into ROMs. Thereafter, the ROMs are finished and sent to the client. The manufacturing process of ROM is very complicated, having many steps, each takes time and must be processed and controlled precisely. Because most ROM elements have the same structure but only differ in the data stored therein during the programing stage, processing steps before programming stage can be performed to produce half-finished products. When an order is placed by the client for storing a specified program into ROMs, a mask for the program can be rapidly produced. The half-finished ROMs can then be programmed and sent to the client as soon as possible. Therefore, post-programmed mask ROMs have become widely used in this art.
The most commonly used structure of ROM is so-called flat-cell structure having buried bit lines because it occupies the least amount of space on a chip, therefore it is very suitable for high-capacity memory applications. However, as known in the art, mask misalignment frequently happens in manufacturing process of integrated circuit (IC). In the ROM coding step, the problems of mask misalignment and lateral diffusion of implanted impurities often cause adjacent cells to be partially turned off (if they are supposed to be "ON" cells) or to have lower read current, especially the cells that are far from the voltage source (V.sub.cc).
More specifically, please refer to FIG. 1 and FIG. 2 which show a conventional ROM structure having buried bit lines. FIG. 2 is a schematic top view of the layout of the ROM. FIG. 1 is a schematic cross-sectional view taken along line I--I in FIG. 2. The conventional ROM includes lateral N.sup.+ source/drain regions 10, which are also termed buried bit lines (BN.sup.+), and longitudinal polysilicon gate regions 12, which are also termed word lines. Channel regions 14 are formed between every two adjacent buried bit lines 10 and underneath stacked gate oxide 16/word lines 12. In the coding step, a photoresist 18 is deposited and then patterned by using a coding mask to expose desired or planned channel regions, like the code areas 20 and 22 as shown in FIGS. 1 and 2. In the drawings, code area 20 shows a misalignment condition. Code area 22 shows the proper alignment condition. After that, ROM code implantation takes place by, for example, implanting B.sup.+ ions into channel regions 14, to disable the coded channel regions permanently.
As stated above, if the coding mask is misaligned, the implanted ions may laterally diffuse into adjacent "ON" memory cells. This may partially turn off the memory cells, reduce their read current and even cause wrong output of coded data.